A manycore vision processor architecture for embedded applications

Silva, Bruno Almeida da; Lima, Arthur Mendes; Silva, Jones Yudi Mori Alves da

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Campo DC	Valor	Lengua/Idioma
dc.contributor.author	Silva, Bruno Almeida da	-
dc.contributor.author	Lima, Arthur Mendes	-
dc.contributor.author	Silva, Jones Yudi Mori Alves da	-
dc.date.accessioned	2021-01-28T19:18:09Z	-
dc.date.available	2021-01-28T19:18:09Z	-
dc.date.issued	2020	-
dc.identifier.citation	SILVA, Bruno Almeida da; LIMA, Arthur Mendes; YUDI, Jones. A manycore vision processor architecture for embedded applications. In: BRAZILIAN SYMPOSIUM ON COMPUTING SYSTEMS ENGINEERING (SBESC), 10., Florianópolis, 2020. p. 1-8. DOI: 10.1109/SBESC51047.2020.9277867. Disponível em: https://ieeexplore.ieee.org/document/9277867.	pt_BR
dc.identifier.uri	https://repositorio.unb.br/handle/10482/39986	-
dc.language.iso	Inglês	pt_BR
dc.publisher	IEEE	pt_BR
dc.rights	Acesso Restrito	pt_BR
dc.title	A manycore vision processor architecture for embedded applications	pt_BR
dc.type	Trabalho	pt_BR
dc.subject.keyword	MPSoC	pt_BR
dc.subject.keyword	NoC	pt_BR
dc.subject.keyword	Processamento de imagens	pt_BR
dc.subject.keyword	Visão por computador	pt_BR
dc.identifier.doi	10.1109/SBESC51047.2020.9277867	pt_BR
dc.relation.publisherversion	https://ieeexplore.ieee.org/document/9277867	pt_BR
dc.description.abstract1	Real-Time Image Processing and Computer Vision systems are now in the mainstream of technologies enabling applications for Cyber-Physical Systems, Internet of Things, Augmented Reality, and Industry 4.0. These applications bring the need for Smart Camera for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a many-core vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed Processing Elements and Memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to four hundred Processing Elements were implemented and compared to several works from the literature. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.	pt_BR
dc.description.unidade	Faculdade de Tecnologia (FT)	-
dc.description.unidade	Departamento de Engenharia Mecânica (FT ENM)	-
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