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Título : A reconfigurable system approach to the direct kinematics of a 5 d.o.f robotic manipulator
Autor : Sánchez Gómez, Diego Felipe
Muñoz Arboleda, Daniel Mauricio
Llanos Quintero, Carlos Humberto
Motta, José Maurício Santos Torres da
Assunto:: Cinemática das máquinas
Computação - robótica
Fecha de publicación : 2010
Editorial : Hindawi Publishing Corporation
Citación : SÁNCHEZ, Diego F. et al. A reconfigurable system approach to the direct kinematics of a 5 d.o.f robotic manipulator. International Journal of Reconfigurable Computing, New York, v. 2010, Article ID 727909, 10 p. 2010. Disponível em: <http://www.hindawi.com/journals/ijrc/2010/727909/>. Acesso em: 04 mar. 2013. doi:10.1155/2010/727909
Resumen : Hardware acceleration in high performance computer systems has a particular interest for many engineering and scientific applications in which a large number of arithmetic operations and transcendental functions must be computed. In this paper a hardware architecture for computing direct kinematics of robot manipulators with 5 degrees of freedom (5 D.o.f ) using floatingpoint arithmetic is presented for 32, 43, and 64 bit-width representations and it is implemented in Field ProgrammableGate Arrays (FPGAs). The proposed architecture has been developed using several floating-point libraries for arithmetic and transcendental functions operators, allowing the designer to select (pre-synthesis) a suitable bit-width representation according to the accuracy and dynamic range, as well as the area, elapsed time and power consumption requirements of the application. Synthesis results demonstrate the effectiveness and high performance of the implemented cores on commercial FPGAs. Simulation results have been addressed in order to compute the Mean Square Error (MSE), using the Matlab as statistical estimator, validating the correct behavior of the implemented cores. Additionally, the processing time of the hardware architecture was compared with the same formulation implemented in software, using the PowerPC (FPGA embedded processor), demonstrating that the hardware architecture speeds-up by factor of 1298 the software implementation.
Licença:: Copyright © 2010 Diego F. Sánchez et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Fonte: http://www.hindawi.com/journals/ijrc/2010/727909/. Acesso em: 04 mar. 2013.
DOI: doi:https://dx.doi.org/10.1155/2010/727909
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